1. Field of the Invention
The present invention relates to a compound semiconductor field effect transistor and a manufacturing method thereof.
2. Description of the Related Background Art
In the recent several years, with the highly-sophisticated and globalized tendency of information, attention has been focused on a mobile communication system in terms of its usability and economical efficiency. In this system, a cordless telephone used on L-band (one frequency band among frequency bands having 1 GHz or higher employed in the mobile communication system) exhibits an abrupt increase in demand. In this cordless telephone, a MMIC (Microwave Monolithic Integrated Circuit) using a compound semiconductor field-effect transistor comprised of a GaAs substrate, etc. is highly desirable.
Further, for obtaining a downsized cordless telephone and a reduction in costs thereof, it is of importance to promote a high integration of the MMIC. Especially, realizing a one-chip front end MMIC in which both a high power output amplifier and a low-noise amplifier of an front end portion are formed on a same chip is important in terms of attaining the downsizing and the reduction in costs of the cordless telephone. It is also of importance for manufacturing such an MIC that the costs are sufficiently low and stability of the manufacturing process is established.
At present, the most popular type of active device for the MMIC is a Schottky junction type field-effect transistor (hereinafter abbreviated to FET) formed of a compound semiconductor substrate. Two known methods of manufacturing this FET are the ion implantation method and the epitaxial method. The ion implantation method has such advantages that the costs are low, element isolation is not required, and a plurality of FETs having different threshold voltages can be simultaneously formed on the same chip.
On the other hand, the epitaxial method has advantages in which a FET having a complicated structure can be formed, and therefore the FET exhibiting a high performance can be obtained. A determination of which process to use depends on the application of the device to be manufactured. In the case of the MMIC in which a multiplicity of FET elements are formed on the same chip, however, there is a tendency to use the ion implantation method. Particularly a self-alignment FET process in which a heat resistant metal is employed for a gate electrode is excellent in terms of a controllability of the threshold voltage and is therefore suited to manufacture an IC. However, a high integration of the MMIC such as a one-chip front end MMIC has been proceeding in recent years. The transistor therein has required a high performance, especially a high gate to drain withstand voltage BV, a high mutual conductance g.sub.m and an excellent low-noise characteristic.
The gate/drain withstand voltage is determined based on a carrier concentration of a semiconductor layer contiguous to the gate electrode and becomes higher with a lower carrier concentration. In case the ion implantation method is used, the withstand voltage is increased by decreasing the dose of the ion implantation or augmenting an acceleration voltage to lower the surface concentration. In this case, however, the withstand voltage is not improved as expected with the reduction of mutual conductance g.sub.m, and as a result there is a limitation in the ion implantation method.
On the other hand, when using the epitaxial method, the degree of freedom to form a complicated structure increases greatly, and therefore a structural design to exhibit a performance responding to a request can be attained. There arise, however, a problem inherent in the epitaxial method when manufacturing the IC constructed of a transistor having two or more kinds of threshold voltages, and it is difficult to actualize the highly integrated MMIC.
For obviating the above-mentioned problems, there can be considered a process in which the ion implantation method and the epitaxial method are combined. That is, the channel layer is formed by the ion implantation method, and the epitaxial layer is formed thereon. The transistor manufactured by this process has an buried channel structure in which the channel is buried. This buried channel structure, because of the channel layer being formed by a selective ion implantation, makes it possible to easily form a plurality of FETs having different threshold voltages on the same ship. Further, there is no necessity for a special process for securing an element-to-element electric insulating property, and, in this respect, the buried channel structure is suited to MMIC applications.
Examples of thus combining the ion implantation method with the epitaxial method are disclosed in Japanese Patent Laid-Open Publication Nos. 62-286284 and 2-98945.
According to the Japanese Patent Laid-Open Publication No. 62-286284, there is disclosed a method in which an ion-implanted layer is formed by implanting ions into a GaAs substrate; an undoped GaAs film is epitaxial-grown on this ion-implanted layer; an anneal for electrically activating the above ion-implanted layer is effected thereafter; and, subsequently, a gate electrode is formed on the undoped GaAs film. In the thus formed FET, it is possible to prevent a dissociation of GaAs in a thermal treatment process with the GaAs film serving as a cap material (protective film), and, besides, because of the cap material being composed of GaAs, a diffusion of Ga from the substrate into the cap layer is also prevented. As a result, a composition of an active layer surface portion formed by the ion implantation does not deviate form a stoichiometric composition, and a GaAs MESFET exhibiting a small fluctuation in threshold value can be obtained.
If a Schottky gate electrode is formed on the remaining GaAs with a film serving as a cap material being left, source and drain regions are formed with this gate electrode serving as a mask, and an impurity is ion-implanted with a high concentration, thereby forming source and drain regions, the impurity in the source and drain regions can be restrained from diffusing just down from the channel region, and the short channel effect can be thereby restrained.
The inventors of the present invention, however, clarified that this method exerts an adverse influence on the operating characteristic. This will be explained later.
On the other hand, according to Japanese Patent Laid-Open Publication No. 2-98945, there is proposed a FET structure in which the ion-implanted layer is formed on an InP substrate; an anneal (protect film annealing) for electrically activating the ion-implanted layer is effected with this ion-implanted layer covered with a protect film; the protect film is thereafter peeled off; an epitaxial layer composed of Al.sub.x Ga.sub.1-x As is formed; and a gate electrode is formed on this Al.sub.x Ga.sub.1-x layer. The substrate composed of InP employed according to this proposal is much more expensive than the GaAs substrate, and it is therefore impossible to attain the reduction in costs by MMIC applications. Further, according to this proposal, the protect film annealing (cap annealing) is employed as an anneal of the ion-implanted layer. In the case of using this protect film annealing, however, the ion-implanted layer surface with a small amount of crystalline defects can not be obtained. The reason is that a multiplicity of crystalline defects exist on the surface of the ion-implanted layer due to the fact that the protect film and ion-implanted layer react on each other at an interface therebetween, and the protect film is exfoliated according to the protect film annealing method. Even when the epitaxial layer is grown on the ion-implanted layer surface on which the multiplicity of crystalline defects exist, the multiplicity of crystalline defects still exist in the vicinity of the interface of the epitaxial layer, and a good interface, i.e., a good electric characteristic can not be obtained.